1. Field of the Invention
The present invention relates in general to built-in/self-test (BIST) circuits and in particular to a BIST circuit for determining whether a path delay within and integrated circuit (IC) is within acceptable limits.
2. Description of Related Art
Integrated circuit (IC) manufacturers often use general purpose IC testers to test ICs by applying test signals to their I/O terminals and monitoring the IC's output signals to see how they respond to the test signal. But as integrated circuits (ICs) have become larger and more complex, IC manufacturers have found it more difficult and time-consuming to use a general purpose IC tester to test every sub-circuit of a large IC. For example, large ICs often include “embedded circuits” such memories that other circuits within an IC access but which are not directly accessible through an IC's I/O terminals and which an external tester therefore cannot directly access. To help reduce testing time and to enable testing of embedded circuits, designers have begun to incorporate built-in self-test (“BIST”) circuits into IC's for testing various circuits within an IC.
For example, a typical BIST circuit for testing a memory includes a “core wrapper” normally linking the memory's terminals to other circuits within the IC that read and write access the memory. However during a test, the core wrapper links the memory terminals to the BIST circuit's memory testing core. After conducting a test, in response to a command from an external device such as a host computer or an IC tester, the BIST circuit returns data to the external device indicating test results. BIST circuits typically communicate with IC terminals via a “scan bus” including a data line interconnecting all of the BIST circuits in daisy chain fashion for serially conveying data into and out of all BIST circuits, a clock line for clocking data through the data line, and one or more control lines connected in parallel to all BIST circuits for indicating when data they have received is valid and other purposes. To tell the BIST circuits to carry out tests, the external host computer shifts commands and control data serially through the data line to scan registers within the BIST circuits and then pulses a control line to tell them that valid data is available in the scan registers. After the BIST circuits have completed their tests, they load test result data into the scan registers and the host computer then shifts test result data back out of the IC via the scan bus data line. Thus using the scan bus, a host computer or external IC test equipment can communicate with many BIST circuits though only a relatively few IC terminals.
An IC can fail to function properly when a delay through a signal path within the IC is too long or too short. U.S. Pat. No. 5,923,676 issued Jul. 13, 1999 to Sunter et al describes a BIST circuit for measuring a delay through a signal path within an IC. During a first test procedure, the BIST circuit connects a reference path across the inputs and outputs of the path under test so that the reference path and the path under test form a first ring oscillator. The BIST circuit counts the number of cycles of a stable reference clock signal that occur during a predetermined number N of cycles of a periodic signal produced by the first ring oscillator. The BIST circuit then passes that first count to an external host computer. During a second test procedure, the BIST circuit connects the reference path's output to its input so that the reference path alone forms a second ring oscillator. The BIST circuit then counts the number of cycles the reference clocks signal that occur during N cycles of the periodic signal produced by the second ring oscillator. The BIST circuit then sends the second count to the external host computer. The external host computer can then compute the delay through the path under test based on the difference between the two counts, the value of N, and the period of the reference clock.
A signal path will typically delay rising and falling edges of a signal by differing amounts due to the lack of symmetry in the switching speeds of logic gates forming the signal path. One drawback to the BIST circuit described by Sunter et al is that the “path delay” that it measures is neither the rising edge delay nor the falling edge delay but the average of the two. In some applications, it is necessary to differentiate between the two types of path delays.
U.S. Pat. No. 6,058,496 issued May 2, 2000 to Gillis et al describes a strobe signal generator for generating first and second strobe signals having edges separated by an adjustable time delay for use in measuring a delay through a signal path in an IC. The first strobe signal edge sends a rising or falling signal edge to the input of the signal path and the other strobe signal tells a latch to sample the state of a resulting signal appearing at the output of the signal path. The state of a data bit stored in the latch indicates whether the delay through the signal path is longer or shorter than the known delay between the first and second strobe signals. The strobe signal generator derives the two strobe signal edges from the same clock signal edge but it passes the second strobe signal edge through a programmable delay circuit that the first strobe signal edge bypasses. Thus, the programmable delay circuit controls the delay between the first and second strobe signal edges.
Gillis teaches a calibration process for adjusting the programmable delay circuit to provide a desired delay between the first and second strobe signal edges wherein the output of the programmable delay circuit is fed back to the strobe signal generator's clock signal input so that the strobe signal generator acts like an oscillator having a period that is equal to the sum of delays though the programmable delay circuit and the inherent path delay in other portions of the feedback loop. With the delay circuit set for “zero delay”, the number of cycles of the oscillator output signal occurring during N cycles of a stable reference clock signal are then counted. The count is saved as a reference value. The delay through the programmable delay circuit is then increased and the number of cycles of the oscillator output signal occurring during N cycle of the reference clock signal are again counted. The difference K between the new cycle count and the reference count is nominally proportional to the delay through the programmable delay circuit, with the known period of the reference clock being the constant of proportionality. Thus, the programmable delay is increased until difference K reaches a value that is expected for the desired strobe delay.
While this system can separately measure rising and falling edge path delays, one difficulty with this system is that during the calibration process, the delay through the programmable delay circuit cannot really be set to zero since all programmable delay circuits have some residual delay when they are at their lowest setting. Thus, the delay provided by the calibration process exceeds the expected delay at least by the amount of the residual delay which can be a considerable amount compared to the path delay to be measured. Another drawback is that the system does not account for differences in path delays the first and second strobe signals may experience as they travel to the latch, so it is important when laying out an IC to make sure that the two paths closely match one another. The calibration circuit taught by Gillis is also relatively complicated, including an arithmetic logic unit, several counters and registers and the like along with sequencing logic capable of controlling operations of all of these parts.
What is needed is a BIST circuit which, like the circuit described in U.S. Pat. No. 6,058,496, can separately measure rising and falling edge delays through a signal path within an IC, but which can do so with greater accuracy and with less complicated hardware.